1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit, and more particularly, to a power-down mode control apparatus for a semiconductor integrated circuit and a DLL (Delay Locked Loop) circuit having the same.
2. Related Art
A conventional DLL circuit supplies an internal clock signal having a more advanced phase than a reference clock signal, which is obtained by converting an external clock signal, for a predetermined time. The internal clock signal that is used in a semiconductor integrated circuit is delayed by a clock signal buffer and a transmission line. Then, a phase difference is generated between the internal clock signal and the external clock signal, causing an output data access time be longer. The DLL circuit is used to solve this problem. In order to increase an effective data output period, the DLL circuit controls the internal clock signal to have a more advanced phase than the external clock signal for a predetermined time.
A recent semiconductor integrated circuit has a power-down mode function for low power consumption. That is, during a period in which the semiconductor integrated circuit does not need to be operated, a power-down mode is activated to cut power supply to internal circuits, thereby reducing power consumption. A DLL circuit which is used in the semiconductor integrated circuit also has a power-down mode function. In this case, when an externally input power-down mode signal is enabled, predetermined constituent elements stop operations.
If the operations of a plurality of constituent elements are stopped simultaneously in response to the power-down mode signal, noise may occur due to a rapid state change in each constituent element. Resultant noise may be accompanied by a jitter component in the locked output clock signal of the DLL circuit, and as a result, an unstable clock signal may be generated. In addition, when the power-down mode is terminated, a delay value which is set before the power-down mode is activated may be changed. Accordingly, the phase of the clock signal may be distorted. As such, if the DLL circuit is erroneously operated, a circuit, such as a data input/output buffer, to which the clock signal is supplied from the DLL circuit, may not normally operate.
The conventional DLL circuit has only a function to simultaneously stop a plurality of constituent elements when the power-down mode is activated, but it still cannot suppress the erroneous operation. Accordingly, during the power-down mode, the DLL circuit is affected by noise. In addition, it is not possible to sufficiently support a semiconductor integrated circuit that can achieve low power consumption during a power-down mode.